1. Field of the Invention
The present invention relates to a method for fabricating an electron tunnel oxide (ETOX) flash memory device with improved coupling efficiency.
2. Description of the Related Art
Coupling efficiency is an important factor that affects the performance of a flash memory. Coupling efficiency can be defined as the amount of floating gate voltage coupled from the control gate voltage. In terms of capacitance, coupling efficiency can also be defined as the ratio of capacitance between the floating gate and the control gate to the total capacitance of the memory cell.
During operation of a flash memory device, the coupling efficiency strongly effects the voltage gained in the floating gate from the control gate. The larger the coupling efficiency of a flash memory device, the larger the value of the voltage at the floating gate. The increased voltage at the floating gate results in increased memory performance of the device.
FIG. 1 is a sectional view of a conventional ETOX flash memory device 2. ETOX device 2 includes a substrate 10, a source region 12, a tunnel oxide 14, a drain region 16, a floating gate 18, an inter-poly dielectric 20 and a control gate 22. The form of device 2 is a stack-gate structure, wherein floating gate 18 and control gate 22 have a self-aligned structure.
FIGS. 2(a) to 2(b) illustrate an example of process steps for the production of conventional ETOX flash memory device 2 as shown in FIG. 1.
FIG. 2(a) shows a first step in the process for making ETOX flash memory device 2. Following field oxidation, tunnel oxide 14 is formed on the surface of substrate 10. Floating gate 18, of polysilicon, is then deposited on tunnel oxide 14. Inter-poly dielectric layer 20 is then deposited on floating gate 18. Next, control gate 22, of polysilicon, is deposited on inter-poly dielectric layer 20.
FIG. 2(b) shows a subsequent step in the process for making ETOX flash memory device 2. A photoresist 24 is deposited on control gate 22 and patterned to conform to the region which will act as the gate structure of ETOX device 2. Etching is then conducted, leaving only those portions of control gate 22, inter-poly dielectric layer 20, floating gate 18 and tunnel oxide 14 which will act as the gate structure of ETOX device 2.
Photoresist 24 is then removed from control gate 22. Finally, source region 12 and drain region 16 are implanted in substrate 10 in the conventional manner. The resulting ETOX device is as shown in FIG. 1.
Conventional ETOX device 2 as shown in FIG. 1 allows the use of a minimum cell area. Further, inter-poly dielectric 20 can be formed to have a thickness approximately the same as tunnel oxide 14, resulting in a coupling efficiency as high as 50%.
In order to achieve a higher coupling efficiency, floating gate 18 can be overlapped by control gate 22. While a coupling efficiency higher than 60% can be achieved by such an overlap, the resulting ETOX device will have a larger cell area than the device of FIG. 1.